1. Technical Field of the Invention
The present invention relates to an improved phase locked loop circuit. More particularly, the instant invention relates to correcting an error condition in the operation of switched capacitor resistance based phase locked loops.
2. Description of Related Art
Phase locked loop (PLL) circuits are used in circuits that require high frequency clock signals. In these circuits, usually the frequency of the clock signal is a multiple of the frequency of a stable low-noise reference signal. PLL circuits are also used in applications where constant tracking of the reference signal is required for the output signal.
PLL circuits are commonly used in transmitters and receivers for locally generating signals for these devices. These signals are commonly used for extracting the channel information at the receiver end. PLL circuits are also used for clock recovery in communication systems, disk drives, etc. Another common application for PLL circuits is found in modulation and demodulation of frequency modulated signals.
A conventional PLL circuit is illustrated in FIG. 1. A conventional PLL comprises a phase frequency detector (PFD) 11, a loop filter 12, a voltage controlled oscillator (VCO) 13 and an N Divider 14. The PFD 11 device receives two inputs and generates an output which represents the phase difference between the two input signals . The first input to the PLL is the external reference input RFCLK on one terminal and while the second input applied to the other port receives the feedback signal FBCLK derived from the final output of the PLL. The output of the PFD 11 is used as the input for a loop filter 12. At this point the filtered output is a DC signal which is fed to the VCO 13. The control input of the VCO 13 is a measure of input frequency and the output of the VCO is a locally generated periodic signal with a frequency which is usually a multiple of the input signal RFCLK. A divider circuit N 14 is provided for the feedback path to produce the feedback signal FBCLK and define the multiplicity of input frequency with respect to the output.
FIG. 2 describes a widely used switched capacitor resistor PLL as shown in U.S. Pat. No. 6,420,917, the disclosure of which is hereby incorporated by reference. The PLL comprises a phase frequency detector 211, a charge pump 212, a loop filter 22 and a voltage controlled oscillator (VCO) 24. Note that the feedback loop of the PLL is not illustrated in FIG. 2. The loop filter 22 is used for connecting the output of the phase frequency detector 211 to a VCO 24. The output of the VCO 24 is the output of the PLL circuit. This is fed back to the phase frequency detector 211 through a divider circuit (not shown). The loop filter 22 is designed to meet the stability criteria so the loop does not enter an oscillatory condition. Different resistive devices are inserted into the loop filter to result is stabilization of the loop. A simple resistor results in excessive background thermal noise.
U.S. Pat. No. 6,420,917 introduces an idea for implementing the passive resistor in the PLL loop filter 22 by using a switched capacitor circuit. As noted in the patent, the sampling clock of this switched capacitor resistor has to be of a frequency which is higher than the PLL loop bandwidth for the switched capacitor resistor to accurately match an equivalent passive resistor. The Patent does not talk about the way in which this sampling clock can be generated. Further, there needs to be a definite phase relationship between this sampling clock and the input clock to the PLL. This relationship is important from the point of view of locking behavior of the PLL when the PLL starts from zero initial voltage at its various internal nodes.
More particularly, if FBCLK leads REFCLK at a particular instant, the state of the switched capacitor circuit would not change until the rising edge of REFCLK, but the charge pump would, depending on the phase difference between FBCLK and REFCLK, remove charge from the loop filter 22. This is an erroneous condition, because after the charge has been removed from the loop filter and before the voltages in the loop filter 22 can settle to their final values, the state of the switched capacitor circuit would change to the other configuration. Ideally, the state of the switched capacitor circuit should change first and only then should the charge be removed from the loop filter 22. If REFCLK leads FBCLK at a particular instant, there would be a finite time delay for the non-overlapping clock generator 213 to generate the required clocks for the switched capacitor resistor. But, if within this delay, the charge pump 212 delivers charge pump to the loop filter 22, it would again be an erroneous condition. This is because the configuration of the switched capacitor circuit when the charge pump 212 delivers charge is the previous configuration. Ideally, the charge should be delivered to the loop filter 22 only after the new configuration of the switched capacitor circuit has been set.
Hence, there is need for a loop filter circuit that will lead to the avoidance of the erroneous condition in the charge pump. There is also need for a circuit for generating the sampling clock in the PLL circuit. There is further need for an improved phase locked loop circuit which addresses the aforesaid drawbacks of the prior art. There is also a need to provide a loop filter for a PLL that will lead to the avoidance of the erroneous condition in the charge pump. There is also a need to provide a circuit for generating the sampling clock in the PLL.